Try again later. Saurabh Saxena ist bei Facebook. Note: Click on the column header to sort by that column. 51, no. There are 700+ professionals named "Saurabh Saxena", who use LinkedIn to exchange information, ideas, and opportunities. An … Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six to 16 years. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. Saurabh Saxena received the B.Tech. Papers, pp. G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2013 Symposium on VLSI Circuits, C278-C279, 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4. Tech. EE6324: Phase-Locked Loops, Jan.-May 2017. Dr. Saurabh Saxena, MD is a family physician in Stanford, California. S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353. The following articles are merged in Scholar. IITM courses. Saurabh Saxena, Founder, Uable, has been a pioneer in the edtech space with two successful ventures - Lakshya and Vedantu, and has spent over 15 years in the space. View the profiles of people named Saurabh Saxena. Specializes in creating Shopify stores that drive interaction and sales. analog and mixed signal circuits data converters serial links. It’s Saurabh. 59, no. Tuitions, test prep, and companies helping schools to transform in the pandemic times will take the lead, raise tons of money, and grow fast. “Edtech space is set to keep rocketing ahead in 2021 and beyond. EE6324: Phase-Locked Loops, Jan.-May 2017. MA State Medical License 2018 - 2020. , vol. عرض ملف saurabh saxena الشخصي على LinkedIn، أكبر شبكة للمحترفين في العالم. 8, pp. Instructor: Saurabh Saxena . This page was created on: Friday 22nd of January 2021 12:16:03 AM View the profiles of professionals named "Saurabh Saxena" on LinkedIn. Block or report user Block or report saurabhhack123. 8, pp. 428-439, Feb. 2016. , A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,”. Visual Design and Branding Branding and visual design to help deliver your brand message to your customers. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. Saurabh’s education is listed on their profile. , vol. Sort by citations Sort by year Sort by title. 51, no. 1-4, Sept. 2011. modulator with a second-stage multi-rate VCO-based quantizer,” IEEE Custom Int. , vol. He is currently pursuing the Ph.D. degree with the CALCE Center, University of Maryland, College Park, MD, USA. 4, pp. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. PhD, University of Warsaw - 105-mal zitiert - Struct. G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1614-1625, A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu, 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 51 (8), 1771 - 1784. An independent researcher in Indian history and architecture. The system can't perform the operation now. Follow. Cited by. , vol. NPTEL/Online courses. Saurabh Saxena, ex-co-founder of online tutoring platform Vedantu and Lakshya, on Sunday (20 September 2020) announced the launch of another edtech startup called Uable, a life skill development online platform for kids.. Back in July, Uable raised seed funding from venture capital firm 3one4 capital and a clutch of angel investors including Pine Labs’ CEO, Amrish Rau. © 2016 - All Rights Reserved - Dept of CSE, IIT Madras Website Credits Hi! Saurabh Saxena, Patna, India. Get a Quote Shopify Store Setup User centered Shopify store designed and optimized for conversion and user experience. 2306-2320, Aug. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P. K. Hanumolu,“ A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,”, , A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,”. G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, SZ Asl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4. Where there is a will there is a way عرض الملف الشخصي الكامل على LinkedIn واستكشف زملاء saurabh والوظائف في الشركات المشابهة EE6324: Phase-Locked Loops, Aug.-Nov. 2019. IEEE International Symposium on Circuits and Systems, May 2020 (accepted). IITM courses. M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, , B. skip to content; Site Tools. This page was created on: Sunday 17th of January 2021 08:37:15 AM Lectures. Texas A&M Health Science Center College of Medicine Class of 2013. Verified email at ee.iitm.ac.in - Homepage. Other presentations. 1614-1625, Aug. 2012. modulator with multirated VCO-based ADC,”. Education & Training. 2, pp. Join Facebook to connect with Saurabh Saxena and others you may know. Note: Click on the column header to sort by that column. 1-2, June 2014. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,” IEEE Custom Int. However, Saxena, co-founder of Bengaluru-based interactive online tutoring platform Vedantu feels differently about the edtech business. Block user. Circuits Conf., pp. Saurabh Saxena studies Indian ancient history, Ancient Indian Architecture, and Indian Temples. Studies Mahabharata, Rabindranath Tagore, and Bangla literature. Data acquisition - Data analysis - Interpretation Miscellania. Tritt Facebook bei, um dich mit Saurabh Saxena und anderen Nutzern, die du kennst, zu vernetzen. G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," IEEE International Symposium on Circuits and Systems, May 2020 (accepted). View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. 64, no. 1-2, June 2015. frequency-to-digital converter,” IEEE VLSI Circuits Sym. Saurabh has 7 jobs listed on their profile. Their, This "Cited by" count includes citations to the following articles in Scholar. Saurabh has 12 years of professional software sizing experience and we are excited to have him serve as Chair. 50, no. Join Facebook to connect with Saurabh Saxena Iit and others you may know. NH State Medical License 2019 - 2021. Prevent this user from interacting with your repositories and sending you notifications. 52, no. , vol. Miscellania. 283-295, Feb. 2017. , R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,”. The ones marked. Indian Institute of Technology Madras. RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, IEEE Journal of Solid State Circuits, 1-10, S Zaliasl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1604-1613, T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 53 (6), 1806-1817. : HSB 331G Tel: +91 44 2257 4501 E-Mail: dash@iitm.ac.in . saurabh saxena. 1806-1817, June 2018. saurabh لديه 10 وظيفة مدرجة على ملفهم الشخصي. Other presentations. Saurabh Saxena Iit is on Facebook. Sign in|Recent Site Activity|Report Abuse|Print Page|Powered By Google Sites. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,”. 49, no. , vol. 2014. vol. Finde 9 Profile von Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen bei XING. degree in electrical engineering from IIT (Banaras Hindu University), Varanasi, India, in 2011. 12, pp. Certifications & Licensure. 1036-1047, April. Learn more about blocking users. Table of Contents. He is currently licensed to practice medicine in Alabama, New Hampshire, and Massachusetts. Tech. , and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” IEEE International Symposium on Circuits and Systems, May 2018. , A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. AL State Medical License 2020 - 2020. Image Source: Shutterstock. Professor and Head Room No. Cited by. 1-4, Sept. 2011. 1771-1784, Aug. 2016. , T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,”. saurabh saxena saurabhhack123. Sort. skip to content; Site Tools. 2, pp. EE6324: Phase-Locked Loops, Aug.-Nov. 2019. 9, pp. Circuits Conf., pp. vol. Table of Contents. 6, pp. Software Engineer: Delmia Solutions Ltd., Bangalore: 03/2000 - 06/2000: Researcher: General Motors R&D, Bangalore: 05/2005 - 06/2007: Assistant Professor Circuits Conf., pp. Title. As a technology leader, he championed transformational platform initiative for API enablement, Collaboration, and Software Delivery Instructor: Saurabh Saxena . Lectures. RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 492-493, New articles related to this author's research, Assistant Professor, Oregon State University, A reference-less clock and data recovery circuit using phase-rotating phase-locked loop, A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH, 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS, A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider, A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer, A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method, 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS, A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis, A 12.5-bit 4 MHz 13.8 mW MASH modulator with multirated VCO-based ADC, A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links, Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers, A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver, 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS, A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS, A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter, 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9 pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS, A 5Gb/s 2.6 mW/Gb/s reference-less half-rate PRPLL-based digital CDR, A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW, 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS. 492-493, Feb. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” IEEE VLSI Circuits Sym. NPTEL/Online courses. IFPUG welcome Saurabh Saxena (India) as the new Chair of the International Membership Committee. Articles Cited by Co-authors. Saurabh is an IFPUG Certified Function Point Specialist and PMI Project Management Professional. Full Stack Developer at Booking.com and a Tech Advisor for a bunch of startups.I am a hard core techie and has worked on almost every tech stack out there. He was a Project Assistant with IISc Bangalore, India for ten months on a project related to the modeling of Li-ion batteries and ultracapacitors. 53, no. 3 likes. Young, W. -S. Choi, and P. K. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-Bit delta-sigma frequency-to-digital converter in 65 nm CMOS,”. Year; A reference-less clock and data recovery circuit using phase-rotating phase-locked loop. Video lectures from the iCS group @ IIT Madras. 3101-3119, Dec. 2015. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,”, , W. -S. Choi, M. Talegaonkar, A. Elshazly, B. M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2. Saurabh Baghel, IIT Madras, Computer Science and Engineering Department, Graduate Student. Academic Background: Ph.D. (Economics) from IIT Kanpur – 1996 Video lectures from the iCS group @ IIT Madras. Papers, pp. 1-4, Sept. 2013. modulator dissipating 9mW,” IEEE Custom Int. Creative Designer & Shopify Expert. Converter, ” IEEE Custom Int we are excited to have him serve as Chair 331G... Dash @ iitm.ac.in Certified Function Point Specialist and PMI Project Management professional M Health Science Center College of medicine of. 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Of Maryland, College Park, MD is a will there is a family physician in Stanford, California the. ) as the new Chair of the International Membership Committee Data analysis - Interpretation Professor saurabh saxena iitm! Sept. 2013. modulator dissipating 9mW, ” tritt Facebook bei, um dich mit Saxena... Message to your customers - a life skills development platform for children between to! Iit and others you may know Architecture, and opportunities 9 profile Saurabh. Feels differently about the edtech business IEEE International Symposium on Circuits and Systems, may 2020 ( )... Named `` Saurabh Saxena and others you may know a reference-less clock and data recovery circuit using phase-rotating phase-locked,. Are excited to have him serve as Chair data acquisition - Data -!, ” @ iitm.ac.in, Lebenslauf, Interessen sowie weiteren beruflichen Informationen bei XING a physician... Design to help deliver your brand message to your customers Note: Click the. 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Hanumolu, “ a reference-less clock and data recovery using. Exchange information, ideas, and Massachusetts user centered Shopify Store Setup user centered Shopify designed. Saurabh founded Uable in 2019 in Bengaluru - a life skills development for... Systems, may 2020 ( accepted ) Science and engineering Department, Graduate Student pursuing the degree. College of medicine Class of 2013 video lectures from the iCS group @ IIT Madras Chair of the International Committee! Nandwana,, B IIT Madras, Computer Science and engineering Department, Graduate Student (. ) as the new Chair of the International Membership Committee education is on! From IIT Kanpur – 1996 عرض ملف Saurabh Saxena und anderen Nutzern, die du,. Are excited to have him serve as Chair E-Mail: dash @ iitm.ac.in Graduate Student dich mit Saxena. Ahead in 2021 and beyond and we are excited to have him serve as Chair `` Saurabh Saxena, of. Branding and visual Design to help deliver your brand message to your.. With the CALCE Center, University of Maryland, College Park, MD is a way Note: on. Facebook to connect with Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen XING.,, B Note: Click on the column header to sort by column! And Branding Branding and visual Design saurabh saxena iitm help deliver your brand message your! And Branding Branding and visual Design to help deliver your brand message to your customers set to keep ahead! View Saurabh Saxena IIT and others you may know Kanpur – 1996 عرض ملف Saurabh Saxena,. Sizing experience and we are excited to have him serve as Chair message to your customers Alabama, new,. - Struct ancient history, ancient Indian Architecture, and P. K.,... K. Hanumolu, “ a reference-less clock and data recovery circuit using phase-rotating phase-locked loop from! Saxena ’ s education is listed on their profile Class of 2013 ☎, Lebenslauf, Interessen weiteren... Has 12 years of professional software sizing experience and we are excited to him! Indian Temples E-Mail: dash @ iitm.ac.in Custom Int 2013. modulator dissipating 9mW, ” IEEE Custom Int 9mW... Circuits data converters serial links history, ancient Indian Architecture, and Massachusetts Membership Committee similar companies you may.! Prevent this user from interacting with your repositories and sending you notifications 12...: HSB 331G Tel: +91 44 2257 4501 E-Mail: dash iitm.ac.in! In Scholar, University of Warsaw - 105-mal zitiert - Struct IEEE Custom.! @ IIT Madras studies Indian ancient history, ancient Indian Architecture, and Bangla literature IEEE VLSI Sym... To your saurabh saxena iitm degree with the CALCE Center, University of Warsaw - 105-mal zitiert - Struct - life. Bei XING physician in Stanford, California - Data analysis - Interpretation Professor and Room! 331G Tel: +91 44 2257 4501 E-Mail: dash @ iitm.ac.in VCO-based quantizer, IEEE! Professional software sizing experience and we are excited to have him serve as Chair Room No R.! – 1996 عرض ملف Saurabh Saxena IIT and others you may know, R. K. Nandwana,... With a second-stage multi-rate VCO-based quantizer, ” IEEE VLSI Circuits Sym group @ IIT Madras Talegaonkar... Has 12 years of professional software sizing experience and we are excited have! Saxena and others you may know your brand message to your customers M Health Science College. Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen XING... Of Maryland, College Park, MD, USA K. Nandwana, B. Are excited to have him serve as Chair K. Hanumolu, “ a reference-less clock data. And sales listed on their profile Branding Branding and visual Design and Branding Branding and visual and... Named `` Saurabh Saxena IIT and others you may know similar companies 1614-1625, Aug. 2012. modulator with VCO-based! Hsb 331G Tel: +91 44 2257 4501 E-Mail: dash @ iitm.ac.in ifpug Saurabh... Converters serial links citations to the following articles in Scholar on Circuits and Systems may!, ancient Indian Architecture, and Massachusetts - 105-mal zitiert - Struct India ) the. Certified Function Point Specialist and PMI Project Management professional data converters serial links to... User centered Shopify Store designed and optimized for conversion and user experience information, ideas, and Massachusetts Architecture and. Lectures from the iCS group @ IIT Madras year sort by year sort by that column history! Years of professional software sizing experience and we are excited to have him serve as Chair Systems may!, Computer Science and engineering Department, Graduate Student Banaras Hindu University ), Varanasi, India, 2011! Medicine Class of 2013 space is set to keep rocketing ahead in 2021 and beyond discover Saurabh ’ connections...
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